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Subject[PATCHv2 0/3] mmc: socfpga: add method to configure clk-phase
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Hi,

This is version 2 of the patchset to configure the clk-phase for the
SDMMC controller on SoCFPGA platforms.

Updates from v1:
- Documented "altr,sysmgr-syscon" binding
- Cleaned up dw_mci_socfpga_priv_init() to get the "clk-phase-sd-hs"
from the DTS. Ulf Hanson recommended using mmc_of_parse_clk_phase() in
this function, however, I found that using mmc_of_parse_clk_phase() is a
bit more complicated than just reading the "clk-phase-sd-hs" from the
DTS. Here are the reasons:
- The call to mmc_of_parse_clk_phase() takes the struct mmc_host
*host structure, and in the dw_mmc driver, and this structure
does not get populated until at the very end of the dw_mci_probe
function, after dw_mci_init_slot() gets called.
- Also, in order to correctly extract the
phase_map.phase[timing], we need to wait until set_ios() is
called in order to get the host->timing parameter so it can be used for
the clock phase array.

Dinh Nguyen (3):
dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon"
arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node
mmc: dw_mmc-pltfm: socfpga: add method to configure clk-phase

.../bindings/mmc/synopsys-dw-mshc.yaml | 8 ++++
.../boot/dts/altera/socfpga_stratix10.dtsi | 1 +
.../dts/altera/socfpga_stratix10_socdk.dts | 1 +
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 1 +
.../boot/dts/intel/socfpga_agilex_socdk.dts | 1 +
.../boot/dts/intel/socfpga_n5x_socdk.dts | 1 +
drivers/mmc/host/dw_mmc-pltfm.c | 41 ++++++++++++++++++-
7 files changed, 53 insertions(+), 1 deletion(-)

--
2.25.1

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