Messages in this thread | | | Date | Fri, 24 Jun 2022 05:37:33 +0800 | From | kernel test robot <> | Subject | [jirislaby:lto 40/45] drivers/cpufreq/amd-pstate.c:127:15: warning: no previous prototype for 'do_amd_pstate_enable' |
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tree: https://git.kernel.org/pub/scm/linux/kernel/git/jirislaby/linux.git lto head: 8047611082d70c5263114fabce8c80a4c3d251fa commit: d6c599165eddb7f2b0f4caa0b5be6c3913bf5cfb [40/45] cpufreq, amd-pstate, lto: Fix for gcc LTO config: x86_64-allyesconfig (https://download.01.org/0day-ci/archive/20220624/202206240521.RzAbNYZb-lkp@intel.com/config) compiler: gcc-11 (Debian 11.3.0-3) 11.3.0 reproduce (this is a W=1 build): # https://git.kernel.org/pub/scm/linux/kernel/git/jirislaby/linux.git/commit/?id=d6c599165eddb7f2b0f4caa0b5be6c3913bf5cfb git remote add jirislaby https://git.kernel.org/pub/scm/linux/kernel/git/jirislaby/linux.git git fetch --no-tags jirislaby lto git checkout d6c599165eddb7f2b0f4caa0b5be6c3913bf5cfb # save the config file mkdir build_dir && cp config build_dir/.config make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/cpufreq/
If you fix the issue, kindly add following tag where applicable Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/cpufreq/amd-pstate.c:127:15: warning: no previous prototype for 'do_amd_pstate_enable' [-Wmissing-prototypes] 127 | __visible int do_amd_pstate_enable(bool enable) | ^~~~~~~~~~~~~~~~~~~~ >> drivers/cpufreq/amd-pstate.c:152:15: warning: no previous prototype for 'do_amd_pstate_init_perf' [-Wmissing-prototypes] 152 | __visible int do_amd_pstate_init_perf(struct amd_cpudata *cpudata) | ^~~~~~~~~~~~~~~~~~~~~~~ >> drivers/cpufreq/amd-pstate.c:200:16: warning: no previous prototype for 'do_amd_pstate_update_perf' [-Wmissing-prototypes] 200 | __visible void do_amd_pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf, | ^~~~~~~~~~~~~~~~~~~~~~~~~
vim +/do_amd_pstate_enable +127 drivers/cpufreq/amd-pstate.c
126 > 127 __visible int do_amd_pstate_enable(bool enable) 128 { 129 return wrmsrl_safe(MSR_AMD_CPPC_ENABLE, enable); 130 } 131 132 static int cppc_enable(bool enable) 133 { 134 int cpu, ret = 0; 135 136 for_each_present_cpu(cpu) { 137 ret = cppc_set_enable(cpu, enable); 138 if (ret) 139 return ret; 140 } 141 142 return ret; 143 } 144 145 DEFINE_STATIC_CALL(amd_pstate_enable, do_amd_pstate_enable); 146 147 static inline int amd_pstate_enable(bool enable) 148 { 149 return static_call(amd_pstate_enable)(enable); 150 } 151 > 152 __visible int do_amd_pstate_init_perf(struct amd_cpudata *cpudata) 153 { 154 u64 cap1; 155 156 int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, 157 &cap1); 158 if (ret) 159 return ret; 160 161 /* 162 * TODO: Introduce AMD specific power feature. 163 * 164 * CPPC entry doesn't indicate the highest performance in some ASICs. 165 */ 166 WRITE_ONCE(cpudata->highest_perf, amd_get_highest_perf()); 167 168 WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1)); 169 WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1)); 170 WRITE_ONCE(cpudata->lowest_perf, AMD_CPPC_LOWEST_PERF(cap1)); 171 172 return 0; 173 } 174 175 static int cppc_init_perf(struct amd_cpudata *cpudata) 176 { 177 struct cppc_perf_caps cppc_perf; 178 179 int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); 180 if (ret) 181 return ret; 182 183 WRITE_ONCE(cpudata->highest_perf, amd_get_highest_perf()); 184 185 WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf); 186 WRITE_ONCE(cpudata->lowest_nonlinear_perf, 187 cppc_perf.lowest_nonlinear_perf); 188 WRITE_ONCE(cpudata->lowest_perf, cppc_perf.lowest_perf); 189 190 return 0; 191 } 192 193 DEFINE_STATIC_CALL(amd_pstate_init_perf, do_amd_pstate_init_perf); 194 195 static inline int amd_pstate_init_perf(struct amd_cpudata *cpudata) 196 { 197 return static_call(amd_pstate_init_perf)(cpudata); 198 } 199 > 200 __visible void do_amd_pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf, 201 u32 des_perf, u32 max_perf, bool fast_switch) 202 { 203 if (fast_switch) 204 wrmsrl(MSR_AMD_CPPC_REQ, READ_ONCE(cpudata->cppc_req_cached)); 205 else 206 wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, 207 READ_ONCE(cpudata->cppc_req_cached)); 208 } 209
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