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Subject[PATCH 1/3] spi: dw: select SS0 when gpio cs is used
Date
SER register contains only 4-bit bit-field for enabling 4 SPI chip selects.
If gpio cs are used the cs number may be >= 4. To ensure we do not write
outside of the valid area, we choose SS0 in case of gpio cs to start
spi transfer.

Co-developed-by: Lukasz Zemla <Lukasz.Zemla@woodward.com>
Signed-off-by: Lukasz Zemla <Lukasz.Zemla@woodward.com>
Signed-off-by: Edmund Berenson <edmund.berenson@emlix.com>
---
drivers/spi/spi-dw-core.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
index 99edddf9958b..57c9e384d6d4 100644
--- a/drivers/spi/spi-dw-core.c
+++ b/drivers/spi/spi-dw-core.c
@@ -94,6 +94,10 @@ void dw_spi_set_cs(struct spi_device *spi, bool enable)
{
struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
bool cs_high = !!(spi->mode & SPI_CS_HIGH);
+ u8 enable_cs = 0;
+
+ if (!spi->cs_gpiod)
+ enable_cs = spi->chip_select;

/*
* DW SPI controller demands any native CS being set in order to
@@ -103,7 +107,7 @@ void dw_spi_set_cs(struct spi_device *spi, bool enable)
* support active-high or active-low CS level.
*/
if (cs_high == enable)
- dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
+ dw_writel(dws, DW_SPI_SER, BIT(enable_cs));
else
dw_writel(dws, DW_SPI_SER, 0);
}
--
2.37.4
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