Messages in this thread | | | Date | Fri, 7 Jan 2022 11:30:26 -1000 | From | Tejun Heo <> | Subject | Re: ata: For what PHY was debounce delay introduced? (was: [PATCH v3 3/3] ahci: AMD A85 FCH (Hudson D4): Skip 200 ms debounce delay in `sata_link_resume()`) |
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Hello,
On Wed, Jan 05, 2022 at 03:49:58PM -0500, Jeff Garzik wrote: > On Tue, Jan 4, 2022 at 6:34 AM Paul Menzel <pmenzel@molgen.mpg.de> wrote: > > > [cc: +jeff, +tejun] > > > > void sata_phy_reset(struct ata_port *ap) > > { > > […] > > /* wait for phy to become ready, if necessary */ > > do { > > msleep(200); > > sstatus = scr_read(ap, SCR_STATUS); > > if ((sstatus & 0xf) != 1) > > break; > > } while (time_before(jiffies, timeout)); > > […] > > } > > ``` > > > > The piix did not have SCRs, as I recall, so it wouldn't apply to those > chips. I don't recall further than that. > > Presumably just give those early chips a "needs delay" quirk, and then > start testing newer chips to make sure they survive an immediate bitbang?
I don't remember exactly but most likely the sata_sil chips, I think. But, yeah, the way forward would be converting it to a quirk and gradually lift them with tests.
Thanks and happy new year.
-- tejun
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