Messages in this thread | | | From | Nadav Amit <> | Subject | Re: [PATCH v5 5/7] iommu/amd: Tailored gather logic for AMD | Date | Tue, 13 Jul 2021 21:52:45 +0000 |
| |
> On Jul 13, 2021, at 11:40 AM, Robin Murphy <robin.murphy@arm.com> wrote: > > On 2021-07-13 10:41, Nadav Amit wrote: >> From: Nadav Amit <namit@vmware.com> >> AMD's IOMMU can flush efficiently (i.e., in a single flush) any range. >> This is in contrast, for instnace, to Intel IOMMUs that have a limit on >> the number of pages that can be flushed in a single flush. In addition, >> AMD's IOMMU do not care about the page-size, so changes of the page size >> do not need to trigger a TLB flush. >> So in most cases, a TLB flush due to disjoint range is not needed for >> AMD. Yet, vIOMMUs require the hypervisor to synchronize the virtualized >> IOMMU's PTEs with the physical ones. This process induce overheads, so >> it is better not to cause unnecessary flushes, i.e., flushes of PTEs >> that were not modified. >> Implement and use amd_iommu_iotlb_gather_add_page() and use it instead >> of the generic iommu_iotlb_gather_add_page(). Ignore disjoint regions >> unless "non-present cache" feature is reported by the IOMMU >> capabilities, as this is an indication we are running on a physical >> IOMMU. A similar indication is used by VT-d (see "caching mode"). The >> new logic retains the same flushing behavior that we had before the >> introduction of page-selective IOTLB flushes for AMD. >> On virtualized environments, check if the newly flushed region and the >> gathered one are disjoint and flush if it is. >> Cc: Joerg Roedel <joro@8bytes.org> >> Cc: Will Deacon <will@kernel.org> >> Cc: Jiajun Cao <caojiajun@vmware.com> >> Cc: Lu Baolu <baolu.lu@linux.intel.com> >> Cc: iommu@lists.linux-foundation.org >> Cc: linux-kernel@vger.kernel.org> >> Cc: Robin Murphy <robin.murphy@arm.com> >> Signed-off-by: Nadav Amit <namit@vmware.com> >> --- >> drivers/iommu/amd/iommu.c | 23 ++++++++++++++++++++++- >> 1 file changed, 22 insertions(+), 1 deletion(-) >> diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c >> index bfae3928b98f..cc55c4c6a355 100644 >> --- a/drivers/iommu/amd/iommu.c >> +++ b/drivers/iommu/amd/iommu.c >> @@ -2048,6 +2048,27 @@ static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, >> return ret; >> } >> +static void amd_iommu_iotlb_gather_add_page(struct iommu_domain *domain, >> + struct iommu_iotlb_gather *gather, >> + unsigned long iova, size_t size) >> +{ >> + /* >> + * AMD's IOMMU can flush as many pages as necessary in a single flush. >> + * Unless we run in a virtual machine, which can be inferred according >> + * to whether "non-present cache" is on, it is probably best to prefer >> + * (potentially) too extensive TLB flushing (i.e., more misses) over >> + * mutliple TLB flushes (i.e., more flushes). For virtual machines the >> + * hypervisor needs to synchronize the host IOMMU PTEs with those of >> + * the guest, and the trade-off is different: unnecessary TLB flushes >> + * should be avoided. >> + */ >> + if (amd_iommu_np_cache && gather->end != 0 && > > iommu_iotlb_gather_is_disjoint() is also checking "gather->end != 0", so I don't think we need both. Strictly it's only necessary here since the other call from iommu_iotlb_gather_add_page() equivalently asserts that the gather is already non-empty via its gather->pgsize check, but one could argue it either way and I don't have a hugely strong preference.
You are correct (even if the compiler would have eliminated the redundancy).
I will remove the redundant check.
> > Otherwise, I love how neat this has all ended up, thanks for persevering!
Thank you for the thorough review!
Regards, Nadav
| |