Messages in this thread Patch in this message | | | From | Wanpeng Li <> | Subject | [PATCH 2/2] KVM: LAPIC: reset TMCCT during vCPU reset | Date | Thu, 3 Jun 2021 02:00:41 -0700 |
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From: Wanpeng Li <wanpengli@tencent.com>
The value of current counter register after reset is 0 for both Intel and AMD, let's do it in kvm.
Signed-off-by: Wanpeng Li <wanpengli@tencent.com> --- arch/x86/kvm/lapic.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 20dd2ae..9ba539b 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -2352,6 +2352,7 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) kvm_lapic_set_reg(apic, APIC_ICR2, 0); kvm_lapic_set_reg(apic, APIC_TDCR, 0); kvm_lapic_set_reg(apic, APIC_TMICT, 0); + kvm_lapic_set_reg(apic, APIC_TMCCT, 0); for (i = 0; i < 8; i++) { kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0); kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0); -- 2.7.4
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