Messages in this thread | | | Subject | Re: [perf] perf_fuzzer causes unchecked MSR access error | From | "Liang, Kan" <> | Date | Wed, 3 Mar 2021 15:00:19 -0500 |
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On 3/3/2021 2:28 PM, Stephane Eranian wrote: > On Wed, Mar 3, 2021 at 10:16 AM Vince Weaver <vincent.weaver@maine.edu> wrote: >> >> Hello >> >> on my Haswell machine the perf_fuzzer managed to trigger this message: >> >> [117248.075892] unchecked MSR access error: WRMSR to 0x3f1 (tried to write 0x0400000000000000) at rIP: 0xffffffff8106e4f4 (native_write_msr+0x4/0x20) >> [117248.089957] Call Trace: >> [117248.092685] intel_pmu_pebs_enable_all+0x31/0x40 >> [117248.097737] intel_pmu_enable_all+0xa/0x10 >> [117248.102210] __perf_event_task_sched_in+0x2df/0x2f0 >> [117248.107511] finish_task_switch.isra.0+0x15f/0x280 >> [117248.112765] schedule_tail+0xc/0x40 >> [117248.116562] ret_from_fork+0x8/0x30 >> >> that shouldn't be possible, should it? MSR 0x3f1 is MSR_IA32_PEBS_ENABLE >> > Not possible, bit 58 is not defined in PEBS_ENABLE, AFAIK. > >> >> this is on recent-git with the patch causing the pebs-related crash >> reverted. >>
We never use bit 58. It should be a new issue. Is it repeatable?
Thanks, Kan
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