Messages in this thread Patch in this message | | | Subject | Re: [perf] perf_fuzzer causes unchecked MSR access error | From | "Liang, Kan" <> | Date | Thu, 4 Mar 2021 14:33:17 -0500 |
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On 3/3/2021 3:22 PM, Vince Weaver wrote: > On Wed, 3 Mar 2021, Liang, Kan wrote: > >> We never use bit 58. It should be a new issue.
Actually, KVM uses it. They create a fake event called VLBR_EVENT, which uses bit 58. It's introduced from the commit 097e4311cda9 ("perf/x86: Add constraint to create guest LBR event without hw counter").
Since it's a fake event, it doesn't support PEBS. Perf should reject it if it sets the precise_ip.
The below patch should fix the MSR access error.
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 5bac48d..1ea3c67 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3659,6 +3659,10 @@ static int intel_pmu_hw_config(struct perf_event *event) return ret;
if (event->attr.precise_ip) { + + if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT) + return -EINVAL; + if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) { event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; if (!(event->attr.sample_type & Thanks, Kan
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