Messages in this thread | | | Subject | Re: [PATCH net] net: dsa: mt7530: setup core clock even in TRGMII mode | From | Florian Fainelli <> | Date | Wed, 10 Mar 2021 19:21:17 -0800 |
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On 3/10/2021 5:21 PM, Ilya Lipnitskiy wrote: > A recent change to MIPS ralink reset logic made it so mt7530 actually > resets the switch on platforms such as mt7621 (where bit 2 is the reset > line for the switch). That exposed an issue where the switch would not > function properly in TRGMII mode after a reset. > > Reconfigure core clock in TRGMII mode to fix the issue. > > Tested on Ubiquiti ER-X (MT7621) with TRGMII mode enabled. > > Fixes: 3f9ef7785a9c ("MIPS: ralink: manage low reset lines") > Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> -- Florian
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