Messages in this thread | | | Date | Wed, 29 Apr 2020 16:22:49 +0200 | From | Boris Brezillon <> | Subject | Re: [PATCH v4 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC |
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On Wed, 29 Apr 2020 18:42:05 +0800 "Ramuthevar, Vadivel MuruganX" <vadivel.muruganx.ramuthevar@linux.intel.com> wrote:
> + > +#define EBU_ADDR_SEL(n) (0x20 + (n) * 4) > +#define EBU_ADDR_MASK (5 << 4)
It's still unclear what ADDR_MASK is for. Can you add a comment explaining what it does?
> +#define EBU_ADDR_SEL_REGEN 0x1
> + > + writel(lower_32_bits(ebu_host->cs[ebu_host->cs_num].nand_pa) | > + EBU_ADDR_SEL_REGEN | EBU_ADDR_MASK, > + ebu_host->ebu + EBU_ADDR_SEL(reg)); > + > + writel(EBU_MEM_BASE_CS_0 | EBU_ADDR_MASK | EBU_ADDR_SEL_REGEN, > + ebu_host->ebu + EBU_ADDR_SEL(0)); > + writel(EBU_MEM_BASE_CS_1 | EBU_ADDR_MASK | EBU_ADDR_SEL_REGEN, > + ebu_host->ebu + EBU_ADDR_SEL(reg));
That's super weird. You seem to set EBU_ADDR_SEL(reg) twice. Are you sure that's needed, and are we setting EBU_ADDR_SEL(0) here?
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