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Subject[RFC v5 25/57] objtool: arm64: Decode calls to higher EL
Date
Decode instructions that volontarily trigger exceptions to a higher
exception level.

It is assumed that the higher exception level should service the request
in a sane maner, returning to the caller exception level without
altering its context too much (e.g. not modifying the PC, the stack
pointer or the frame pointer).

Suggested-by: Raphael Gault <raphael.gault@arm.com>
Signed-off-by: Julien Thierry <jthierry@redhat.com>
---
tools/objtool/arch/arm64/decode.c | 45 +++++++++++++++++++
.../objtool/arch/arm64/include/insn_decode.h | 2 +
2 files changed, 47 insertions(+)

diff --git a/tools/objtool/arch/arm64/decode.c b/tools/objtool/arch/arm64/decode.c
index c38d73fb57e1..aa00de725686 100644
--- a/tools/objtool/arch/arm64/decode.c
+++ b/tools/objtool/arch/arm64/decode.c
@@ -419,6 +419,11 @@ static struct aarch64_insn_decoder br_sys_decoder[] = {
.value = 0b1100100010000000000000,
.decode_func = arm_decode_system_regs,
},
+ {
+ .mask = 0b1111100000000000000000,
+ .value = 0b1100000000000000000000,
+ .decode_func = arm_decode_except_gen,
+ },
};

int arm_decode_br_sys(u32 instr, enum insn_type *type,
@@ -486,3 +491,43 @@ int arm_decode_system_regs(u32 instr, enum insn_type *type,
*type = INSN_OTHER;
return 0;
}
+
+int arm_decode_except_gen(u32 instr, enum insn_type *type,
+ unsigned long *immediate, struct list_head *ops_list)
+{
+ u32 imm16 = 0;
+ unsigned char opc = 0, op2 = 0, LL = 0, decode_field = 0;
+
+ imm16 = (instr >> 5) & ONES(16);
+ opc = (instr >> 21) & ONES(3);
+ op2 = (instr >> 2) & ONES(3);
+ LL = instr & ONES(2);
+ decode_field = (opc << 5) | (op2 << 2) | LL;
+
+#define INSN_SVC 0b00000001
+#define INSN_HVC 0b00000010
+#define INSN_SMC 0b00000011
+
+ switch (decode_field) {
+ case INSN_SVC:
+ case INSN_HVC:
+ case INSN_SMC:
+ /*
+ * We consider that the context will be restored correctly
+ * with an unchanged sp and the same general registers
+ */
+ *type = INSN_NOP;
+ return 0;
+ default:
+ return arm_decode_unknown(instr, type, immediate, ops_list);
+ }
+
+#undef INSN_SVC
+#undef INSN_HVC
+#undef INSN_SMC
+#undef INSN_BRK
+#undef INSN_HLT
+#undef INSN_DCPS1
+#undef INSN_DCPS2
+#undef INSN_DCPS3
+}
diff --git a/tools/objtool/arch/arm64/include/insn_decode.h b/tools/objtool/arch/arm64/include/insn_decode.h
index 777a62f1a141..a55dcbfcfed2 100644
--- a/tools/objtool/arch/arm64/include/insn_decode.h
+++ b/tools/objtool/arch/arm64/include/insn_decode.h
@@ -70,4 +70,6 @@ int arm_decode_system_insn(u32 instr, enum insn_type *type,
int arm_decode_system_regs(u32 instr, enum insn_type *type,
unsigned long *immediate,
struct list_head *ops_list);
+int arm_decode_except_gen(u32 instr, enum insn_type *type,
+ unsigned long *immediate, struct list_head *ops_list);
#endif /* _ARM_INSN_DECODE_H */
--
2.21.0
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