Messages in this thread | | | From | Etienne Carriere <> | Date | Wed, 22 Jan 2020 19:20:01 +0100 | Subject | Re: [PATCH v11 2/2] mailbox: introduce ARM SMC based mailbox |
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Hello Peng and all,
> From: Peng Fan <peng.fan@nxp.com> > > This mailbox driver implements a mailbox which signals transmitted data > via an ARM smc (secure monitor call) instruction. The mailbox receiver > is implemented in firmware and can synchronously return data when it > returns execution to the non-secure world again. > An asynchronous receive path is not implemented. > This allows the usage of a mailbox to trigger firmware actions on SoCs > which either don't have a separate management processor or on which such > a core is not available. A user of this mailbox could be the SCP > interface. > > Modified from Andre Przywara's v2 patch > https://lore.kernel.org/patchwork/patch/812999/ > > Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> > Reviewed-by: Andre Przywara <andre.przywara@arm.com> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
I've successfully tested your change on my board. It is a stm32mp1 with TZ secure hardening and I run an OP-TEE firmware (possibly a TF-A sp_min) with a SCMI server for clock and reset. Upstream in progress. The platform uses 2 instances of your SMC based mailbox device driver (2 mailboxes). Works nice with your change.
You can add my T-b tag: Tested-by: Etienne Carriere <etienne.carriere@linaro.org>
FYI, I'll (hopefully soon) post a change proposal in U-Boot ML for an equvalent 'SMC based mailbox' driver and SCMI agent protocol/device drivers for clock and reset controllers. I'm also working on getting this SCMI server upstream in TF-A and OP-TEE. Your SMC based mailbox driver is a valuable notification scheme for our SCMI services support in Arm TZ secure world.
Regards, Etienne
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