Messages in this thread | | | Date | Fri, 2 Aug 2019 08:37:12 +0200 | From | Christoph Hellwig <> | Subject | DMA_ATTR_WRITE_COMBINE on mips |
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[I hope the imgtec address still works, but maybe the mips folks know if it moved to mips]
Hi Alex,
you added DMA_ATTR_WRITE_COMBINE support in dma_mmap_attrs to mips in commit 8c172467be36f7c9591e59b647e4cd342ce2ef41 ("MIPS: Add implementation of dma_map_ops.mmap()"), but that commit only added the support in mmap, not in dma_alloc_attrs. This means the memory is now used in kernel space through KSEG1, and thus uncached, while for userspace mappings through dma_mmap_* pgprot_writebombine is used, which creates a write combine mapping, which on some MIPS CPUs sets the _CACHE_UNCACHED_ACCELERATED pte bit instead of the _CACHE_UNCACHED one. I know at least on arm, powerpc and x86 such mixed page cachability attributes can cause pretty severe problems. Are they ok on mips? Or was the DMA_ATTR_WRITE_COMBINE supported unintended and not correct and we should remove it?
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