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SubjectRe: [RFC PATCH 05/16] RISC-V: KVM: Implement VCPU interrupts and requests handling
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On 30/07/19 14:45, Anup Patel wrote:
> Here's some text from RISC-V spec regarding SIP CSR:
> "software interrupt-pending (SSIP) bit in the sip register. A pending
> supervisor-level software interrupt can be cleared by writing 0 to the SSIP bit
> in sip. Supervisor-level software interrupts are disabled when the SSIE bit in
> the sie register is clear."
>
> Without RISC-V hypervisor extension, the SIP is essentially a restricted
> view of MIP CSR. Also as-per above, S-mode SW can only write 0 to SSIP
> bit in SIP CSR whereas it can only be set by M-mode SW or some HW
> mechanism (such as S-mode CLINT).

But that's not what the spec says. It just says (just before the
sentence you quoted):

A supervisor-level software interrupt is triggered on the current
hart by writing 1 to its supervisor software interrupt-pending (SSIP)
bit in the sip register.

and it's not written anywhere that S-mode SW cannot write 1. In fact
that text is even under sip, not under mip, so IMO there's no doubt that
S-mode SW _can_ write 1, and the hypervisor must operate accordingly.

In fact I'm sure that if Windows were ever ported to RISC-V, it would be
very happy to use that feature. On x86, Intel even accelerated it
specifically for Microsoft. :)

Paolo

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