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SubjectRe: [PATCH v2 04/11] soc: pmc: Add blink output clock registration to Tegra PMC
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27.11.2019 07:59, Sowjanya Komatineni пишет:
> Tegra PMC has blink control to output 32 Khz clock out to Tegra
> blink pin. Blink pad DPD state and enable controls are part of
> Tegra PMC register space.
>
> Currently Tegra clock driver registers blink control by passing
> PMC address and register offset to clk_register_gate which performs
> direct PMC access during clk_ops and with this when PMC is in secure
> mode, any access from non-secure world does not go through.
>
> This patch adds blink control registration to the Tegra PMC driver
> using PMC specific clock gate operations that use tegra_pmc_readl
> and tegra_pmc_writel to support both secure mode and non-secure
> mode PMC register access.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> drivers/soc/tegra/pmc.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 49 insertions(+)
>
> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
> index a353f6d0a832..1cfb7797dbd5 100644
> --- a/drivers/soc/tegra/pmc.c
> +++ b/drivers/soc/tegra/pmc.c
> @@ -61,12 +61,15 @@
> #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
> #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
> #define PMC_CNTRL_PWRREQ_POLARITY BIT(8)
> +#define PMC_CNTRL_BLINK_EN BIT(7)
> #define PMC_CNTRL_MAIN_RST BIT(4)
>
> #define PMC_WAKE_MASK 0x0c
> #define PMC_WAKE_LEVEL 0x10
> #define PMC_WAKE_STATUS 0x14
> #define PMC_SW_WAKE_STATUS 0x18
> +#define PMC_DPD_PADS_ORIDE 0x1c
> +#define PMC_DPD_PADS_ORIDE_BLINK BIT(20)
>
> #define DPD_SAMPLE 0x020
> #define DPD_SAMPLE_ENABLE BIT(0)
> @@ -79,6 +82,7 @@
>
> #define PWRGATE_STATUS 0x38
>
> +#define TEGRA210_PMC_BLINK_TIMER 0x40

This register is common for all Tegra SoCs, therefore TEGRA210_ prefix
isn't needed.

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