Messages in this thread | | | From | Logan Gunthorpe <> | Date | Tue, 22 Oct 2019 16:01:19 -0600 | Subject | [PATCH v2 0/2] AMD IOMMU Changes for NTB |
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Hi,
Please find the following patches which help support Non-Transparent-Bridge (NTB) devices on AMD platforms with the IOMMU enabled.
These patches add support for multiple PCI aliases. NTB hardware will normally send TLPs from a range of requestor IDs to facilitate routing the responses back to the correct requestor on the other side of the bridge. To support this, NTB hardware registers a number of PCI aliases. Currently the AMD IOMMU only allows for one PCI alias so TLPs from the other aliases get rejected.
See commit ad281ecf1c7d ("PCI: Add DMA alias quirk for Microsemi Switchtec NTB") for more information on this.
Similar patches were upstreamed for Intel hardware earlier this year:
commit 3f0c625c6ae7 ("iommu/vt-d: Allow interrupts from the entire bus for aliased devices")
Thanks,
Logan
--
Changes since v1: * Dropped the first patch as similar functionality has already been added with the generic iommu interface * Rebased onto joro/iommu.git next branch * Reworked the set_remap_table_entry_alias() function to also do the flushing by getting the iommu from amd_iommu_rlookup_table (per suggestion from Joerg)
Logan Gunthorpe (2): iommu/amd: Support multiple PCI DMA aliases in device table iommu/amd: Support multiple PCI DMA aliases in IRQ Remapping
drivers/iommu/amd_iommu.c | 170 +++++++++++++++++--------------- drivers/iommu/amd_iommu_types.h | 2 +- 2 files changed, 92 insertions(+), 80 deletions(-)
-- 2.20.1
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