Messages in this thread | | | Date | Wed, 03 May 2017 18:30:04 -0700 | From | Sodagudi Prasad <> | Subject | gic_write_grpen1 in hotplug flow |
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Hi All,
This is regarding the usage of gic_write_grpen1 API usage in irq-gic-v3 driver.
Here my understanding about ICC_IGRPEN1_EL1. ICC_IGRPEN1_EL1 is banked between secure and non-secure states. If two secure states are implemented, Secure side Group bit is set by the platform firmware (PSCI) and kernel need to set in non secure state. https://mail.codeaurora.org/?_task=mail&_action=compose&_id=676833541590a775943df6# 1) Currently gic_write_grpen1(0) is getting called from gic_cpu_pm_notifier() for CPU_PM_ENTER in single security state only. But enabling of group1 non-secure interrupts are done in CPU_PM_EXIT path unconditionally. Why are we not disabling group1 non-secure interrupts unconditionally in CPU_PM_ENTER(and disabling only in single security state)?
2) Why group1 non-secure interrupts are not disabled in kernel during cpu hotplug path? Spurious interrupt can still come if we dont disable group1 non-secure interrupts, right?
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