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Subjectx86/tsc: Set X86_FEATURE_TSC_RELIABLE to skip refined calibration
Unlike PIT based calibration which counts TSC cycles against another timer,
MSR or CPUID method has no calibration - it simply multiplies the known
frequency of a timer by a ratio. So TSC frequency computed by MSR or CPUID
is the final frequency and doesn't need the refined calibration process.
We used to use set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE) but
it actually doesn't skip refined calibration because the flag is cleared
later in identify_cpu(). A cpu caps flag is not cleared only if it's set
by setup_force_cpu_cap(). This patch sets the flag in tsc_msr.c and
replaces set_cpu_cap() with setup_force_cpu_cap() in other files.

Signed-off-by: Bin Gao <bin.gao@intel.com>
---
arch/x86/kernel/tsc_msr.c | 2 ++
arch/x86/platform/intel-mid/mfld.c | 2 +-
arch/x86/platform/intel-mid/mrfl.c | 2 +-
3 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index 9911a06..52223aa 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -122,6 +122,8 @@ unsigned long try_msr_calibrate_tsc(void)
lapic_timer_frequency = (freq * 1000) / HZ;
pr_info("lapic_timer_frequency = %d\n", lapic_timer_frequency);
#endif
+
+ setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
return res;

fail:
diff --git a/arch/x86/platform/intel-mid/mfld.c b/arch/x86/platform/intel-mid/mfld.c
index 1eb47b6..c75e7a4 100644
--- a/arch/x86/platform/intel-mid/mfld.c
+++ b/arch/x86/platform/intel-mid/mfld.c
@@ -50,7 +50,7 @@ static unsigned long __init mfld_calibrate_tsc(void)
pr_debug("read penwell tsc %lu khz\n", fast_calibrate);
lapic_timer_frequency = fsb * 1000 / HZ;
/* mark tsc clocksource as reliable */
- set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE);
+ setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);

return fast_calibrate;
}
diff --git a/arch/x86/platform/intel-mid/mrfl.c b/arch/x86/platform/intel-mid/mrfl.c
index bd1adc6..aa49531 100644
--- a/arch/x86/platform/intel-mid/mrfl.c
+++ b/arch/x86/platform/intel-mid/mrfl.c
@@ -79,7 +79,7 @@ static unsigned long __init tangier_calibrate_tsc(void)
lapic_timer_frequency);

/* mark tsc clocksource as reliable */
- set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE);
+ setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);

return fast_calibrate;
}
--
1.9.1

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