Messages in this thread | | | Date | Wed, 15 Jun 2016 19:18:00 +0200 | From | Peter Zijlstra <> | Subject | Re: [RFC PATCH-tip v2 1/6] locking/osq: Make lock/unlock proper acquire/release barrier |
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On Wed, Jun 15, 2016 at 04:04:46PM +0800, Boqun Feng wrote: > On Tue, Jun 14, 2016 at 06:48:04PM -0400, Waiman Long wrote:
> > @@ -198,7 +198,7 @@ void osq_unlock(struct optimistic_spin_queue *lock) > > * Second most likely case. > > */ > > node = this_cpu_ptr(&osq_node); > > - next = xchg(&node->next, NULL); > > + next = xchg_release(&node->next, NULL); > > if (next) { > > WRITE_ONCE(next->locked, 1); > > So we still use WRITE_ONCE() rather than smp_store_release() here? > > Though, IIUC, This is fine for all the archs but ARM64, because there > will always be a xchg_release()/xchg() before the WRITE_ONCE(), which > carries a necessary barrier to upgrade WRITE_ONCE() to a RELEASE.
Not sure. On PPC for example, you'll use lwsync() but will that not attach to the store to &node->next instead?
Still leaving that store and the WRITE_ONCE() unordered.
Also I don't see the control dependency between xchg-load and WRITE_ONCE helping anything to order the two stores.
So yeah, subtle if not broken, definitely needs more explanation.
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