Messages in this thread Patch in this message | | | From | Heikki Krogerus <> | Subject | [PATCH] clk: fractional-divider: support for divider bypassing | Date | Mon, 2 Feb 2015 15:37:04 +0200 |
| |
If the divider or multiplier values values are 0 in the register, bypassing the divider and returning the parent clock rate in clk_fd_recalc_rate().
Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> --- drivers/clk/clk-fractional-divider.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c index dc91da7..34d6c51 100644 --- a/drivers/clk/clk-fractional-divider.c +++ b/drivers/clk/clk-fractional-divider.c @@ -36,6 +36,9 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw, m = (val & fd->mmask) >> fd->mshift; n = (val & fd->nmask) >> fd->nshift; + if (!n || !m) + return parent_rate; + ret = (u64)parent_rate * m; do_div(ret, n); -- 2.1.4
| |