Messages in this thread Patch in this message | | | Date | Mon, 27 Aug 2012 04:53:02 +0800 | From | Hein Tibosch <> | Subject | [PATCH 1/2] dw_dmac: make driver endianness configurable |
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The dw_dmac was originally developed for avr32 to be used with the Synopsys DesignWare AHB DMA controller. After 2.6.38, device access was done with the little-endian readl/writel functions. This didn't work on the avr32 platform, because it needs native-endian (i.e. big-endian) accessors. This patch makes the endianness configurable using 'DW_DMAC_BE', which will default be true for AVR32
Signed-off-by: Hein Tibosch <hein_tibosch@yahoo.es> --- drivers/dma/Kconfig | 8 ++++++++ drivers/dma/dw_dmac_regs.h | 23 +++++++++++++++++++++++ 2 files changed, 31 insertions(+), 0 deletions(-)
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index aadeb5b..3635daf 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -89,6 +89,14 @@ config DW_DMAC Support the Synopsys DesignWare AHB DMA controller. This can be integrated in chips such as the Atmel AT32ap7000. +config DW_DMAC_BE + bool "Synopsys DesignWare AHB DMA needs big endian access" + default y if AVR32 + depends on DW_DMAC + help + Say yes if access to the Synopsys DesignWare AHB DMA controller + should be big endian, such as for Atmel AT32ap7000 + config AT_HDMAC tristate "Atmel AHB DMA support" depends on ARCH_AT91 diff --git a/drivers/dma/dw_dmac_regs.h b/drivers/dma/dw_dmac_regs.h index f298f69..cf048c3 100644 --- a/drivers/dma/dw_dmac_regs.h +++ b/drivers/dma/dw_dmac_regs.h @@ -175,11 +175,22 @@ __dwc_regs(struct dw_dma_chan *dwc) return dwc->ch_regs; } +#ifdef CONFIG_DW_DMAC_BE + +#define channel_readl(dwc, name) \ + ioread32be(&(__dwc_regs(dwc)->name)) +#define channel_writel(dwc, name, val) \ + iowrite32be((val), &(__dwc_regs(dwc)->name)) + +#else + #define channel_readl(dwc, name) \ readl(&(__dwc_regs(dwc)->name)) #define channel_writel(dwc, name, val) \ writel((val), &(__dwc_regs(dwc)->name)) +#endif + static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan) { return container_of(chan, struct dw_dma_chan, chan); @@ -201,11 +212,23 @@ static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw) return dw->regs; } +#ifdef CONFIG_DW_DMAC_BE + +#define dma_readl(dwc, name) \ + ioread32be(&(__dw_regs(dw)->name)) +#define dma_writel(dwc, name, val) \ + iowrite32be((val), &(__dw_regs(dw)->name)) + +#else + #define dma_readl(dw, name) \ readl(&(__dw_regs(dw)->name)) #define dma_writel(dw, name, val) \ writel((val), &(__dw_regs(dw)->name)) +#endif + #define channel_set_bit(dw, reg, mask) \ dma_writel(dw, reg, ((mask) << 8) | (mask)) #define channel_clear_bit(dw, reg, mask) \ -- 1.7.8.0
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