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SubjectRe: [PATCH 2/3 v2] gpio: Add support for Intel ICHx/3100/Series[56] GPIO
On Tue, 07 Feb 2012 13:58:31 -0600 (CST), Aaron Sierra wrote:
> This driver works on many Intel chipsets, including the ICH6, ICH7,
> ICH8, ICH9, ICH10, 3100, Series 5/3400 (Ibex Peak), Series 6/C200
> (Cougar Point), and NM10 (Tiger Point).
>
> Additional Intel chipsets should be easily supported if needed, eg the
> ICH1-5, EP80579, etc.
>
> Tested on QM67 (Cougar Point), QM57 (Ibex Peak), 3100 (Whitmore Lake),
> and NM10 (Tiger Point).
> (...)
> +static int ichx_write_bit(int reg, unsigned nr, int val, int verify)
> +{
> + unsigned long flags;
> + u32 data, tmp;
> + int reg_nr = nr / 32;
> + int bit = nr & 0x1f;
> + int ret = 0;
> +
> + spin_lock_irqsave(&ichx_priv.lock, flags);
> +
> + data = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
> + data = (data & ~(1 << bit)) | (val << bit);

I posted a fix for this function last Sunday:

Subject: [PATCH] gpio-ich: Fix setting GPIO value
Date: Sun, 5 Feb 2012 21:44:44 +0100

Please apply it, otherwise your driver doesn't implement the gpio
driver API properly and code running on top of it (consumer drivers)
may fail.

> + ICHX_WRITE(data, ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
> + tmp = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
> + if (verify && (data != tmp))
> + ret = -EPERM;
> +
> + spin_unlock_irqrestore(&ichx_priv.lock, flags);
> +
> + return ret;
> +}

--
Jean Delvare


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