Messages in this thread | | | Date | Mon, 05 Sep 2011 15:49:14 +0100 | From | Jonathan Cameron <> | Subject | Regmap bulk read styles. |
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Hi Mark,
I'm looking at the using your regmap stuff for IIO. Other than the minor queries in the other emails I've sent, the big issue for me is that of bulk reading.
The two most common forms we have are 'burst read' and what might be termed a 'gather read'.
The burst read is pretty much what you have covered by regmap_bulk_read. I assume an implementation for spi doing
TX Addr1 XXXXX XXXXX XXXXX XXXXX RX XXXXX Data1 Data2 Data3 Data4 ...
would be general enough to be worth providing? Any device that doesn't understand this should simply not use it.
The second is more interesting. It actually looks quite like your gather write. We have a set of registers that we need to read. A classic example is that a coherent set will only be received (e.g. valid at an instant in time) if we read all channels of an accelerometer in one go (between chip selects).
typically involves either
TX Addr1 Addr2 Addr3 XXXXX RX XXXXX Data1 Data2 Data3
Or
TX Addr1 00000 Addr2 00000 RX XXXXX Data1 XXXXX Data2
One slight complexity is cs_change, but that probably needs fixing in the spi core which doesn't currently allowing setting up a default for that. This second case would be a set of transfers (read then writes effectively).
Would you be in favour of an interface to handle this use case or is it better just to bypass regmap for this use case? (which would be a pity as it leads to duplication as all the configuration stuff fits nicely).
As an aside, isn't your gather write more typically described as a scatter write? (writes one coherent set to a number of disjoint locations?)
Alternatively should I just be bypassing regmap entirely for read only data registers like these? Caching is kind of pointless other than for debugging purposes (though that would be nice).
Thanks,
Jonathan
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