Messages in this thread | | | Subject | Re: [PATCH 1/4] perf: Add memory load/store events generic code | From | Lin Ming <> | Date | Tue, 05 Jul 2011 19:54:20 +0800 |
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On Mon, 2011-07-04 at 19:16 +0800, Peter Zijlstra wrote: > On Mon, 2011-07-04 at 08:02 +0000, Lin Ming wrote: > > +#define MEM_STORE_DCU_HIT (1ULL << 0) > > I'm pretty sure that's not Dublin City University, but what is it? > Data-Cache-Unit? what does that mean, L1/L2 or also L3? > > > +#define MEM_STORE_STLB_HIT (1ULL << 1) > > What's an sTLB? I know iTLB and dTLB's but sTLBs I've not heard of yet. > > > +#define MEM_STORE_LOCKED_ACCESS (1ULL << 2) > > Presumably that's about LOCK'ed ops? > > So now you're just tacking bits on the end without even attempting to > generalize/unify things, not charmed at all.
Any idea on the more useful store bits encoding?
Thanks, Lin Ming
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