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    Subject[PATCH 0/4] perf: memory load/store events generalization
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    Hi, all

    Intel PMU provides 2 facilities to monitor memory operation: load latency and precise store.
    This patchset tries to generalize memory load/store events.
    So other arches may also add such features.

    A new sub-command "mem" is added,

    $ perf mem

    usage: perf mem [<options>] {record <command> |report}

    -t, --type <type> memory operations(load/store)
    -L, --latency <n> latency to sample(only for load op)

    $ perf mem -t load record make -j8

    <building kernel ..., monitoring memory load opeartion>

    $ perf mem -t load report

    Memory load operation statistics
    ================================
    L1-local: total latency= 28027, count= 3355(avg=8)
    L2-snoop: total latency= 1430, count= 29(avg=49)
    L2-local: total latency= 124, count= 8(avg=15)
    L3-snoop, found M: total latency= 452, count= 4(avg=113)
    L3-snoop, found no M: total latency= 0, count= 0(avg=0)
    L3-snoop, no coherency actions: total latency= 875, count= 18(avg=48)
    L3-miss, snoop, shared: total latency= 0, count= 0(avg=0)
    L3-miss, local, exclusive: total latency= 0, count= 0(avg=0)
    L3-miss, local, shared: total latency= 0, count= 0(avg=0)
    L3-miss, remote, exclusive: total latency= 0, count= 0(avg=0)
    L3-miss, remote, shared: total latency= 0, count= 0(avg=0)
    Unknown L3: total latency= 0, count= 0(avg=0)
    IO: total latency= 0, count= 0(avg=0)
    Uncached: total latency= 464, count= 30(avg=15)

    $ perf mem -t store record make -j8

    <building kernel ..., monitoring memory store opeartion>

    $ perf mem -t store report

    Memory store operation statistics
    =================================
    data-cache hit: 8138
    data-cache miss: 0
    STLB hit: 8138
    STLB miss: 0
    Locked access: 0
    Unlocked access: 8138

    Any comment is appreciated.

    Thanks,
    Lin Ming


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