Messages in this thread | | | Date | Tue, 26 Jul 2011 11:16:56 -0700 | From | "H. Peter Anvin" <> | Subject | Re: [PATCH] x86, AMD: Correct F15h IC aliasing issue |
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On 07/26/2011 11:13 AM, Borislav Petkov wrote: > Hi Avi, > > On Tue, Jul 26, 2011 at 01:59:04PM -0400, Avi Kivity wrote: >>> This change leaves virtual region address allocation on other families >>> and/or vendors unaffected. >>> >> >> Is it possible to derive the bit positions (and the need to mask them) >> from the cpuid description of the cache topology and sizes? > > As far as I understand your question, there's no need for deriving the > bit positions because they're not special. You just have to have bits > [14:12] the same across all processes - we simply opted for clearing > them in order to keep the patch as simple as possible. But we could just > as well hashed the library name and generated the bits from it and thus > keep them same per library (we have that version too, btw. :)). > > FWIW, in both cases, the patch should fix even the virtualization > scenario with and without KSM. > > Does that answer your question? >
I think the question was the width (and position) for the mask... i.e. your [14:12] above which *is* magic.
-hpa
-- H. Peter Anvin, Intel Open Source Technology Center I work for Intel. I don't speak on their behalf.
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