Messages in this thread | | | Date | Tue, 26 Jul 2011 20:37:21 +0200 | From | Borislav Petkov <> | Subject | Re: [PATCH] x86, AMD: Correct F15h IC aliasing issue |
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On Tue, Jul 26, 2011 at 02:16:56PM -0400, H. Peter Anvin wrote: > >> Is it possible to derive the bit positions (and the need to mask them) > >> from the cpuid description of the cache topology and sizes? > > > > As far as I understand your question, there's no need for deriving the > > bit positions because they're not special. You just have to have bits > > [14:12] the same across all processes - we simply opted for clearing > > them in order to keep the patch as simple as possible. But we could just > > as well hashed the library name and generated the bits from it and thus > > keep them same per library (we have that version too, btw. :)). > > > > FWIW, in both cases, the patch should fix even the virtualization > > scenario with and without KSM. > > > > Does that answer your question? > > > > I think the question was the width (and position) for the mask... i.e. > your [14:12] above which *is* magic.
Oh, that's easy: family 15h means bits [14:12] - those bits are used for I$ index generation.
-- Regards/Gruss, Boris.
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