Messages in this thread | | | Date | Mon, 18 Jul 2011 09:30:56 +0400 | Subject | Spinlock assembly clarification | From | Frank Coldwell <> |
| |
dear friends,
I was looking at spinlock implementation in x86 architecture folder and this is code i found there: ----------------------------------------------------------------------------------------------------- static __always_inline void __ticket_spin_lock(arch_spinlock_t *lock) { short inc = 0x0100;
asm volatile ( LOCK_PREFIX "xaddw %w0, %1\n" "1:\t" "cmpb %h0, %b0\n\t" "je 2f\n\t" "rep ; nop\n\t" "movb %1, %b0\n\t" /* don't need lfence here, because loads are in-order */ "jmp 1b\n" "2:" : "+Q" (inc), "+m" (lock->slock) : : "memory", "cc"); } -----------------------------------------------------------------------------------------------------
So to understand this I look at intel manual for these instructions, and I could not find anything for instruction xaddw ??
So can anyone can help me understand what this assembly code is doing and also where are these assembly instructions converted to real assembly instructions (in gcc maybe) ??
Thanks in advance,
| |