lkml.org 
[lkml]   [2011]   [Feb]   [15]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    /
    Date
    SubjectRe: [PATCH 0/2] jump label: 2.6.38 updates
    From
    On Tue, Feb 15, 2011 at 1:31 PM, H. Peter Anvin <hpa@zytor.com> wrote:
    > On 02/15/2011 03:01 AM, Will Newton wrote:
    >>
    >> The CPU in question has two sets of instructions:
    >>
    >>   load/store - these go via the cache (write through)
    >>   ll/sc - these operate literally as if there is no cache (they do not
    >> hit on read or write)
    >>
    >> This may or may not be a sensible way to architect a CPU, but I think
    >> it is possible to make it work. Making it work efficiently is more of
    >> a challenge.
    >>
    >
    > a) What "CPU in question" is this?

    http://imgtec.com/meta/meta-technology.asp

    > b) Why should we let this particular insane CPU slow ALL OTHER CPUs down?

    I didn't propose we do that. I brought it up just to make people aware
    that there are these odd architectures out there, and indeed it turns
    out Blackfin has some superficially similar issues.
    --
    To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
    the body of a message to majordomo@vger.kernel.org
    More majordomo info at http://vger.kernel.org/majordomo-info.html
    Please read the FAQ at http://www.tux.org/lkml/

    \
     
     \ /
      Last update: 2011-02-15 15:07    [W:0.039 / U:29.360 seconds]
    ©2003-2016 Jasper Spaans. hosted at Digital OceanAdvertise on this site