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SubjectRe: [PATCH 0/2] jump label: 2.6.38 updates
On Tue, Feb 15, 2011 at 1:31 PM, H. Peter Anvin <> wrote:
> On 02/15/2011 03:01 AM, Will Newton wrote:
>> The CPU in question has two sets of instructions:
>>   load/store - these go via the cache (write through)
>>   ll/sc - these operate literally as if there is no cache (they do not
>> hit on read or write)
>> This may or may not be a sensible way to architect a CPU, but I think
>> it is possible to make it work. Making it work efficiently is more of
>> a challenge.
> a) What "CPU in question" is this?

> b) Why should we let this particular insane CPU slow ALL OTHER CPUs down?

I didn't propose we do that. I brought it up just to make people aware
that there are these odd architectures out there, and indeed it turns
out Blackfin has some superficially similar issues.
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