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    SubjectRe: [PATCH 0/2] jump label: 2.6.38 updates
    On 13:27 Tue 15 Feb     , David Miller wrote:
    > From: Will Simoneau <>
    > Date: Tue, 15 Feb 2011 16:11:23 -0500
    > > Note how the cache and cache coherence protocol are fundamental parts of this
    > > operation; if these instructions simply bypassed the cache, they *could not*
    > > work correctly - how do you detect when the underlying memory has been
    > > modified?
    > The issue here isn't L2 cache bypassing, it's local L1 cache bypassing.
    > The chips in question aparently do not consult the local L1 cache on
    > "ll" instructions.
    > Therefore you must only ever access such atomic data using "ll"
    > instructions.

    (I should not have said "underlying memory", since it is correct that
    only the L1 caches are the problem here)

    That's some really crippled hardware... it does seem like *any* loads
    from *any* address updated by an sc would have to be done with ll as
    well, else they may load stale values. One could work this into
    atomic_read(), but surely there are other places that are problems.

    It would be OK if the caches on the hardware in question were to
    back-invalidate matching cachelines when the sc is snooped from the bus,
    but it sounds like this doesn't happen?
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      Last update: 2011-02-15 22:59    [W:0.020 / U:227.248 seconds]
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