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SubjectRe: [PATCHv5] DMAEngine: Define interleaved transfer request api
On 14 October 2011 20:36, Vinod Koul <> wrote:
>> 2011/10/14 Vinod Koul <>:
>> > On Fri, 2011-10-14 at 17:21 +0530, Jassi Brar wrote:
>> >> On 14 October 2011 13:02, Barry Song <> wrote:
>> >> >
>> >> > what if i want a cyclic interleaved transfer? i think the cyclic
>> >> > interleaved transfer is what i want for audio dma.
>> >> >
>> >> ... we need to restore 'bool frm_irq' and add new 'bool cyclic' that
>> >> would replay the transfer(i.e, reset dma-pointers to src_start & dst_start)
>> >> after 'numf' frames have been transferred.
>> > I was thinking more on lines to have this conveyed thru a flag.
>> >
>> > Anyway I plan to work on merging device_prep_slave_sg and
>> > device_prep_cyclic to single API. Think more of device_prep_cyclic as
>> > special case with sg length one and flag to tell dmac its cyclic.
>> >
>> > Similarly here we could use/define this flag to say this transfer is
>> > also cyclic in nature and dmac then reloads the list again.
>> > That way any prep can be made cyclic in nature by just using this flag.
>> >
>> > @Barry: Why would you need to use interleaved API for audio?
>> At first, audio dma is typically cyclic. if no underflow and overflow
>> happens, it will always be running. underflow and overflow will
>> trigger the cyclic dma termination.
> Yes and you terminate dma. Then prepare will be called again and you
> setup DMA again and on trigger start you start DMA again.
> No need for interleaving in this case.
>> in case audio PCM data is interleaved and saved in dma buffer  as below:
>> left (2B)  right (2B)  left (2B)  right (2B)   left (2B)  right (2B)
>> left (2B)  right (2B)
>> left (2B)  right (2B)  left (2B)  right (2B)   left (2B)  right (2B)
>> left (2B)  right (2B)
>> left (2B)  right (2B)  left (2B)  right (2B)   left (2B)  right (2B)
>> left (2B)  right (2B)
>> left (2B)  right (2B)  left (2B)  right (2B)   left (2B)  right (2B)
>> left (2B)  right (2B)
>> ,,,,
>> and some hardwares need two seperate dma channels to tranfer left and
>> right audio channel.
>> For 1st and 2nd dma channel, they want dma address increases 4bytes
>> and transfer 2bytes every line.
>> so it looks to me like a cyclic interleaved dma.
> Hmmm, do we have sound cards which use this?
> Nevertheless for this kind of transfers we would need interleaved cyclic
> DMA as well, Do you have such usage? Can you tell me which codec
> requires this?
My proposed 'frm_irq' and 'cyclic' flags are for such requirements.

Consider a 5.1chan I2S controller that employs 3 dma-channels
each transferring 2 audio-channels to 3 three FIFOs. And the
pcm-dma driver supports SNDRV_PCM_INFO_INTERLEAVED.
While I worked with simple single fifo 5.1chan I2S controllers, I don't
think such 3-fifo controllers can't exist.
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