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Subject[PATCH] PCI: Add Bridge Configuration Retry bit in PCIE Control
Date
From 7d8f4016eac2ac2877412b6c510616da4e08415e Mon Sep 17 00:00:00 2001
From: Sheng Yang <sheng.yang@intel.com>
Date: Thu, 10 Jul 2008 11:43:33 +0800
Subject: [PATCH] PCI: Add Bridge Configuration Retry bit in PCIE
Control

The bit 15 is Bridge Configuration Retry Reset and Initiate Function
Level Reset bit.

Signed-off-by: Sheng Yang <sheng.yang@intel.com>
---
include/linux/pci_regs.h | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index c0c1223..36ce86b 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -387,6 +387,7 @@
#define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable
*/
#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
+#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration
Retry / FLR */
#define PCI_EXP_DEVSTA 10 /* Device Status */
#define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
#define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
--
1.5.6
From 7d8f4016eac2ac2877412b6c510616da4e08415e Mon Sep 17 00:00:00 2001
From: Sheng Yang <sheng.yang@intel.com>
Date: Thu, 10 Jul 2008 11:43:33 +0800
Subject: [PATCH] PCI: Add Bridge Configuration Retry bit in PCIE Control

The bit 15 is Bridge Configuration Retry Reset and Initiate Function Level Reset
bit.

Signed-off-by: Sheng Yang <sheng.yang@intel.com>
---
include/linux/pci_regs.h | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index c0c1223..36ce86b 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -387,6 +387,7 @@
#define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
+#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
#define PCI_EXP_DEVSTA 10 /* Device Status */
#define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
#define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
--
1.5.6
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