Messages in this thread | | | Date | Wed, 17 Dec 2008 02:56:01 +0100 | From | Samuel Thibault <> | Subject | Re: [Perfctr-devel] [patch] Performance Counters for Linux, v4 |
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Andi Kleen, le Wed 17 Dec 2008 02:51:54 +0100, a écrit : > William Cohen <wcohen@redhat.com> writes: > > PERF_COUNT_CACHE_REFERENCES and PERF_COUNT_CACHE_MISSES are not single > > monolitic events on many processors. There are multiple cache > > levels. The L1 cache most processors have separate instruction and > > data caches and require multiple counters to implement. Would these > > refer to the last level of cache before memory and just be used to > > compute the hit/miss rate for that last level? Some processors in the > > same family have L2 and some processors have L3 cache. The setup code > > would need to distinguish between these processor variants. > > The difference between L1 and L3 caches can be huge (in some cases > two orders of magnitude). With that I'm not sure a single cache > miss/hit event even makes any sense.
Confirmed. I have a code for which I'd like to know whether it fits into at least L2 or even L1.
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