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SubjectRe: [Perfctr-devel] [patch] Performance Counters for Linux, v4
William Cohen <> writes:
> monolitic events on many processors. There are multiple cache
> levels. The L1 cache most processors have separate instruction and
> data caches and require multiple counters to implement. Would these
> refer to the last level of cache before memory and just be used to
> compute the hit/miss rate for that last level? Some processors in the
> same family have L2 and some processors have L3 cache. The setup code
> would need to distinguish between these processor variants.

The difference between L1 and L3 caches can be huge (in some cases
two orders of magnitude). With that I'm not sure a single cache
miss/hit event even makes any sense.

On a modern CPU with L2 and L3 caches as soon as you fall out
of the L2 you're going to perform more poorly on parallel workloads.

With that you really have to distingush some levels.



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