Messages in this thread | | | Date | Wed, 19 Dec 2007 20:40:32 +0100 | From | Ingo Molnar <> | Subject | Re: [PATCH] x86: Voluntary leave_mm before entering ACPI C3 |
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* H. Peter Anvin <hpa@zytor.com> wrote:
> Ingo Molnar wrote: >> * Venki Pallipadi <venkatesh.pallipadi@intel.com> wrote: >> >>> Aviod TLB flush IPIs during C3 states by voluntary leave_mm() before >>> entering C3. >>> >>> The performance impact of TLB flush on C3 should not be significant with >>> respect to C3 wakeup latency. Also, CPUs tend to flush TLB in hardware >>> while in C3 anyways. >>> > > Are there any CPUs around which *don't* flush the TLB across C3? (I > guess it's not guaranteed by the spec, though, and as TLBs grow larger > there might be incentive to keep them online.)
i dont think it's required for C3 to even turn off any portion of the CPU - if an interrupt arrives after the C3 sequence is initiated but just before dirty cachelines have been flushed then the CPU can just return without touching anything (such as the TLB) - right? So i dont think there's any implicit guarantee of TLB flushing (nor should there be), but in practice, a good C3 sequence would (statistically) turn off large portions of the CPU and hence the TLB as well.
Ingo
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