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SubjectRe: question regarding cacheline size
Matthew Wilcox wrote:
> On Thu, Sep 07, 2006 at 02:53:57PM +0200, Tejun Heo wrote:
>> The spec says that devices can put additional restriction on supported
>> cacheline size (IIRC, the example was something like power of two >= or
>> <= certain size) and should ignore (treat as zero) if unsupported value
>> is written. So, there might be need for more low level driver
>> involvement which knows device restrictions, but I don't know whether
>> such devices exist.
> That's nothing we can do anything about. The system cacheline size is
> what it is. If the device doesn't support it, we can't fall back to a
> different size, it'll cause data corruption. So we'll just continue on,
> and devices which live up to the spec will act as if we hadn't
> programmed a cache size. For devices that don't, we'll have the quirk.

For MWI, it will cause data corruption. For READ LINE and MULTIPLE, I
think it would be okay. The memory is prefetchable after all. Anyways,
this shouldn't be of too much problem and probably can be handled by
quirks if ever needed.

> Arguably devices which don't support the real system cacheline size
> would only get data corruption if they used MWI, so we only have to
> prevent them from using MWI; they could use a different cacheline size
> for MRM and MRL without causing data corruption. But I don't think we
> want to go down that route; do you?

Oh yeah, that's what I was trying to say, and I don't want to go down
that route. So, I guess this one is settled.


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