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    SubjectRe: question regarding cacheline size
    Grant Grundler wrote:
    > hrm...if the driver can put a safe value in cachelinesize register
    > and NOT enable MWI, I can imagine a significant performance boost
    > if the device can use MRM or MRL. But IMHO it's up to the driver
    > writers (or other contributors) to figure that out.


    > Current API (pci_set_mwi()) ties enabling MRM/MRL with enabling MWI
    > and I don't see a really good reason for that. Only the converse
    > is true - enabling MWI requires setting cachelinesize.

    Correct, that's why it was done that way, when I wrote the API.
    Enabling MWI required making sure the BIOS configured our CLS for us,
    which was often not the case. No reason why we can't do a

    pdev->set_cls = 1;
    rc = pci_enable_device(pdev);


    rc = pci_set_cacheline_size(pdev);



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      Last update: 2006-09-07 18:07    [W:0.020 / U:11.976 seconds]
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