Messages in this thread | | | From | David Howells <> | Subject | Re: Uses for memory barriers | Date | Tue, 12 Sep 2006 10:01:43 +0100 |
| |
Paul E. McKenney <paulmck@us.ibm.com> wrote:
> 2. All stores to a given single memory location will be perceived > as having occurred in the same order by all CPUs.
Does that take into account a CPU combining or discarding coincident memory operations?
For instance, a CPU asked to issue two writes to the same location may discard the first if it hasn't done it yet.
David - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
| |