Messages in this thread | | | Date | Mon, 11 Sep 2006 13:29:08 -0700 | From | "Paul E. McKenney" <> | Subject | Re: Uses for memory barriers |
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On Mon, Sep 11, 2006 at 09:48:42PM +0200, Oliver Neukum wrote: > Am Montag, 11. September 2006 18:21 schrieb Paul E. McKenney: > > 1. A given CPU will always perceive its own memory operations > > as occuring in program order. > > Is this true for physical memory if virtually indexed caches are > involved?
As I understand it, in systems with virtually indexed caches, the OS must take care to ensure that a given cacheline appears only once in the cache, even if it is mapped to multiple virtual addresses. If an OS failed to do this, then, as far as I can see, all bets are off. Curt Schimmel's book "UNIX(R) Systems for Modern Architectures: Symmetric Multiprocessing and Caching for Kernel Programmers" is an excellent guide to the issues posed by virtually indexed and virtually tagged caches.
In principle, one could construct a virtually indexed/tagged CPU cache that automatically ejected any line with a conflicting physical address (given that lookups are presumably much more frequent than loading new cache lines), but I have no idea if any real hardware takes this approach. I have had the good fortune to always work with physically tagged/indexed caches. ;-)
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