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    SubjectRe: [PATCH] Define wc_wmb, a write barrier for PCI write combining
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    On Tue, 2006-02-28 at 20:33 +0100, Andi Kleen wrote:

    > Anyways if MFENCE improved performance you're probably relying
    > on some very specific artifact of the microarchitecture of your
    > CPU or Northbridge. I don't think it's a architecurally guaranteed
    > feature.

    I looked this up, and you appear to be wrong here.

    Here's the appropriate quote from page 246 of the PDF of "AMD64
    Architecture Programmer's Manual Volume 2: System Programming":

    http://www.amd.com/us-en/assets/content_type/DownloadableAssets/dwamd_24593.pdf

    Section 7.4.1 specifically describes what happens to write buffers:

    [...] the processor completely empties the write buffer by
    writing the contents to memory as a result of performing any of
    the following operations:

    SFENCE Instruction
    Executing a store-fence (SFENCE) instruction forces all memory
    writes before the SFENCE (in program order) to be written into
    memory before memory writes that follow the SFENCE instruction.
    The memory-fence (MFENCE) instruction has a similar effect, but
    it forces the ordering of loads in addition to stores.
    [...]

    So in fact SFENCE is the appropriate, architecturally guaranteed, thing
    for us to be doing on x86_64.

    With respect to Ben's contention that wmb() will suffice instead, that
    isn't true, either, even on x86-class hardware. The writes absolutely
    travel over the HT bus in non-ascending order on AMD64 systems unless we
    fence them, and we've verified this using a HT bus analyser.

    <b

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