Messages in this thread | | | From | Andi Kleen <> | Subject | Re: [PATCH] Define wc_wmb, a write barrier for PCI write combining | Date | Wed, 1 Mar 2006 20:27:54 +0100 |
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On Wednesday 01 March 2006 20:20, Bryan O'Sullivan wrote:
> > [...] the processor completely empties the write buffer by > writing the contents to memory as a result of performing any of > the following operations: > > SFENCE Instruction > Executing a store-fence (SFENCE) instruction forces all memory > writes before the SFENCE (in program order) to be written into > memory before memory writes that follow the SFENCE instruction. > The memory-fence (MFENCE) instruction has a similar effect, but > it forces the ordering of loads in addition to stores. > [...] > > So in fact SFENCE is the appropriate, architecturally guaranteed, thing > for us to be doing on x86_64.
I don't interpret it as being a full synchronous write. It's just a barrier preventing reordering. So the writes before could be in theory stuck forever in some buffer - it just means they won't be later than the writes after the fence.
Implementing the fences in the way your're suggesting would be very costly because it could make them potentially stall for thousands of cycles.
I don't have a quote handy right now but volume 3 of the Intel/AMD manuals have own chapters on the memory ordering rules elaborating on this in much more detail.
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