Messages in this thread | | | Date | Mon, 9 Aug 2004 13:58:22 +0200 (CEST) | From | "Maciej W. Rozycki" <> | Subject | Re: [PATCH] x86 bitops.h commentary on instruction reordering |
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On Fri, 6 Aug 2004, Marcelo Tosatti wrote:
> Yes correct. *mb() usually imply barrier(). > > About the flush, each architecture defines its own instruction for doing so, > PowerPC has "sync" and "isync" instructions (to flush the whole cache and instruction > cache respectively), MIPS has "sync" and so on..
JFTR, in the absence of an external write-back buffer (which some processors have) the MIPS "sync" instruction has exactly the semantics of mb(). There is no MIPS instruction to perform writeback, invalidation, etc. operations on whole caches -- such operations can only be performed in the kernel mode on a line-by-line basis and are model-specific, though some standardisation exists.
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