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SubjectRe: [PATCH] x86 bitops.h commentary on instruction reordering
On Fri, Aug 06, 2004 at 07:36:25PM +0400, Vladislav Bolkhovitin wrote:
> Thanks.
> One more question, if you don't object. How after some variable
> assigment to make other CPUs *immediatelly* see the assigned value, i.e.
> to make current CPU immediately flush its write cache in memory? *mb()
> seems deal with reordering, barrier() with the compiler optimization (am
> I right?).

Yes correct. *mb() usually imply barrier().

About the flush, each architecture defines its own instruction for doing so,
PowerPC has "sync" and "isync" instructions (to flush the whole cache and instruction
cache respectively), MIPS has "sync" and so on..

> The similar memory barrier spin_lock() does, but it's not
> easy to uderstand its internal magic.

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