Messages in this thread | | | Date | Thu, 8 Jan 2004 09:39:49 -0800 | Subject | Re: [RFC] Relaxed PIO read vs. DMA write ordering | From | (Jesse Barnes) |
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On Thu, Jan 08, 2004 at 08:23:49AM -0800, Leonid Grossman wrote: > > I interpret this to mean: > > Setting the RO bit in the PCI-X Command Register only enables > > the device to choose when to set RO Attribute bit when the device > > generates a PCI-X bus cycle. > > Yes, this is exactly how (at least our 10GbE) PCI-X ASICs work. > If the RO bit is set, the device decides whether the transaction > requires strong ordering, > and sets RO attribute accordingly.
Excellent, a card in the wild that actually does this! :) Ok, now I'll take of my sn2 tunnel vision glasses--we don't want another readX variant, but it sounds like we'll need pcix_enable_relaxed() _and_ pci_sync_consistent() to support non-coherent platforms well. How does that sound?
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