Messages in this thread Patch in this message | | | Subject | [PATCH 2.4.23-pre2] PCI quirk for SMBus bridge on Asus P4 boards | Date | Wed, 3 Sep 2003 09:00:40 +0200 (CEST) | From | (Marcel Holtmann) |
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Hi Marcelo,
this has been in 2.5 for some time now and I think it can be added to 2.4 too.
Regards
Marcel
You can import this changeset into BK by piping this whole message to: '| bk receive [path to repository]' or apply the patch as usual.
===================================================================
ChangeSet@1.1131, 2003-09-03 08:42:53+02:00, marcel@holtmann.org [PATCH] PCI quirk for SMBus bridge on Asus P4 boards Asus hides the SMBus PCI bridge within the ICH2 or ICH4 southbridge on Asus P4 mainboards. The attached patch adds a quirk to re-enable the SMBus PCI bridge for P4B533, P4T533, P4PE and P4G8X Deluxe mainboards. Original patch for 2.5 from Dominik Brodowski <linux@brodo.de>
drivers/pci/quirks.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++++ include/linux/pci_ids.h | 4 ++ 2 files changed, 70 insertions(+)
diff -Nru a/drivers/pci/quirks.c b/drivers/pci/quirks.c --- a/drivers/pci/quirks.c Wed Sep 3 08:54:00 2003 +++ b/drivers/pci/quirks.c Wed Sep 3 08:54:00 2003 @@ -648,6 +648,62 @@ } /* + * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge + * is not activated. The myth is that Asus said that they do not want the + * users to be irritated by just another PCI Device in the Win98 device + * manager. (see the file prog/hotplug/README.p4b in the lm_sensors + * package 2.7.0 for details) + * + * The SMBus PCI Device can be activated by setting a bit in the ICH LPC + * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it + * becomes necessary to do this tweak in two steps -- I've chosen the Host + * bridge as trigger. + */ + +static int __initdata asus_hides_smbus = 0; + +static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev) +{ + if (likely(dev->subsystem_vendor != PCI_VENDOR_ID_ASUSTEK)) + return; + + if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) + switch(dev->subsystem_device) { + case 0x8070: /* P4B */ + case 0x8088: /* P4B533 */ + asus_hides_smbus = 1; + } + if ((dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) && + (dev->subsystem_device == 0x80b2)) /* P4PE */ + asus_hides_smbus = 1; + if ((dev->device == PCI_DEVICE_ID_INTEL_82850_HB) && + (dev->subsystem_device == 0x8030)) /* P4T533 */ + asus_hides_smbus = 1; + if ((dev->device == PCI_DEVICE_ID_INTEL_7205_0) && + (dev->subsystem_device == 0x8070)) /* P4G8X Deluxe */ + asus_hides_smbus = 1; + return; +} + +static void __init asus_hides_smbus_lpc(struct pci_dev *dev) +{ + u16 val; + + if (likely(!asus_hides_smbus)) + return; + + pci_read_config_word(dev, 0xF2, &val); + if (val & 0x8) { + pci_write_config_word(dev, 0xF2, val & (~0x8)); + pci_read_config_word(dev, 0xF2, &val); + if(val & 0x8) + printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val); + else + printk(KERN_INFO "PCI: Enabled i801 SMBus device\n"); + } +} + +/* * The main table of quirks. */ @@ -724,6 +780,16 @@ { PCI_FIXUP_FINAL, PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_APIC, quirk_amd_8131_ioapic }, #endif + + /* + * on Asus P4B boards, the i801SMBus device is disabled at startup. + */ + { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge }, + { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge }, + { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge }, + { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge }, + { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc }, + { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc }, { 0 } }; diff -Nru a/include/linux/pci_ids.h b/include/linux/pci_ids.h --- a/include/linux/pci_ids.h Wed Sep 3 08:54:00 2003 +++ b/include/linux/pci_ids.h Wed Sep 3 08:54:00 2003 @@ -1768,6 +1768,7 @@ #define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221 #define PCI_DEVICE_ID_INTEL_82092AA_1 0x1222 #define PCI_DEVICE_ID_INTEL_7116 0x1223 +#define PCI_DEVICE_ID_INTEL_7205_0 0x255d #define PCI_DEVICE_ID_INTEL_82596 0x1226 #define PCI_DEVICE_ID_INTEL_82865 0x1227 #define PCI_DEVICE_ID_INTEL_82557 0x1229 @@ -1780,6 +1781,7 @@ #define PCI_DEVICE_ID_INTEL_82380FB 0x124b #define PCI_DEVICE_ID_INTEL_82439 0x1250 #define PCI_DEVICE_ID_INTEL_80960_RP 0x1960 +#define PCI_DEVICE_ID_INTEL_82845_HB 0x1a30 #define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000 #define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010 #define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020 @@ -1868,6 +1870,8 @@ #define PCI_DEVICE_ID_INTEL_ESB_11 0x25ac #define PCI_DEVICE_ID_INTEL_ESB_12 0x25ad #define PCI_DEVICE_ID_INTEL_ESB_13 0x25ae +#define PCI_DEVICE_ID_INTEL_82850_HB 0x2530 +#define PCI_DEVICE_ID_INTEL_82845G_HB 0x2560 #define PCI_DEVICE_ID_INTEL_80310 0x530d #define PCI_DEVICE_ID_INTEL_82810_MC1 0x7120 #define PCI_DEVICE_ID_INTEL_82810_IG1 0x7121 ===================================================================
This BitKeeper patch contains the following changesets: + ## Wrapped with gzip_uu ##
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