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Subject[patch] AGP3 experimental support
  Hi,

this is port of AGP3 support from 2.6.0-test9. I ported _agp3 functions and
rewrite via_generic_setup(). It seems working, but mybe is necessary to check
AGP3 tests and rewrite agp_generic_enable() function.
Sugestions are welcome.
Regards,
--
-------------------------------------------------------
David "Dave" Jez Brno, CZ, Europe
E-mail: dave.jez@seznam.cz
PGP key: finger xjezda00@eva.fit.vutbr.cz
---------=[ ~EOF ]=------------------------------------

linux/drivers/char/agp/agp.h | 9 +++++++++
linux/drivers/char/agp/agpgart_be.c | 147 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++---
2 files changed, 153 insertions(+), 3 deletions(-)

diff -urN linux.orig/drivers/char/agp/agp.h linux/drivers/char/agp/agp.h
--- linux.orig/drivers/char/agp/agp.h Mon Nov 24 16:19:35 2003
+++ linux/drivers/char/agp/agp.h Mon Nov 24 19:57:36 2003
@@ -332,6 +332,9 @@
#define PCI_DEVICE_ID_ATI_RS300_200 0x5833
#endif

+/* Chipset independant registers (from AGP Spec) */
+#define AGP_APBASE 0x10
+
/* intel register */
#define INTEL_APBASE 0x10
#define INTEL_APSIZE 0xb4
@@ -442,6 +445,12 @@
#define VIA_GARTCTRL 0x80
#define VIA_APSIZE 0x84
#define VIA_ATTBASE 0x88
+
+/* VIA KT400 */
+#define VIA_AGP3_GARTCTRL 0x90
+#define VIA_AGP3_APSIZE 0x94
+#define VIA_AGP3_ATTBASE 0x98
+#define VIA_AGPSEL 0xfd

/* SiS registers */
#define SIS_APBASE 0x10
diff -urN linux.orig/drivers/char/agp/agpgart_be.c linux/drivers/char/agp/agpgart_be.c
--- linux.orig/drivers/char/agp/agpgart_be.c Mon Nov 24 16:20:07 2003
+++ linux/drivers/char/agp/agpgart_be.c Mon Nov 24 19:58:30 2003
@@ -2790,6 +2790,72 @@

#ifdef CONFIG_AGP_VIA

+static int via_fetch_size_agp3(void)
+{
+ int i;
+ u16 temp;
+ aper_size_info_16 *values;
+
+ values = A_SIZE_16(agp_bridge.aperture_sizes);
+ pci_read_config_word(agp_bridge.dev, VIA_AGP3_APSIZE, &temp);
+ temp &= 0xfff;
+
+ for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+ if (temp == values[i].size_value) {
+ agp_bridge.previous_size =
+ agp_bridge.current_size = (void *) (values + i);
+ agp_bridge.aperture_size_idx = i;
+ return values[i].size;
+ }
+ }
+ return 0;
+}
+
+static int via_configure_agp3(void)
+{
+ u32 temp;
+ aper_size_info_16 *current_size;
+
+ current_size = A_SIZE_16(agp_bridge.current_size);
+
+ /* address to map too */
+ pci_read_config_dword(agp_bridge.dev, AGP_APBASE, &temp);
+ agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+
+ /* attbase - aperture GATT base */
+ pci_write_config_dword(agp_bridge.dev, VIA_AGP3_ATTBASE,
+ agp_bridge.gatt_bus_addr & 0xfffff000);
+
+ /* 1. Enable GTLB in RX90<7>, all AGP aperture access needs to fetch
+ * translation table first.
+ * 2. Enable AGP aperture in RX91<0>. This bit controls the enabling of
+the
+ * graphics AGP aperture for the AGP3.0 port.
+ */
+ pci_read_config_dword(agp_bridge.dev, VIA_AGP3_GARTCTRL, &temp);
+ pci_write_config_dword(agp_bridge.dev, VIA_AGP3_GARTCTRL,
+ temp | (3<<7));
+ return 0;
+}
+
+static void via_cleanup_agp3(void)
+{
+ aper_size_info_16 *previous_size;
+
+ previous_size = A_SIZE_16(agp_bridge.previous_size);
+ pci_write_config_byte(agp_bridge.dev, VIA_APSIZE,
+ previous_size->size_value);
+}
+static void via_tlbflush_agp3(agp_memory *mem)
+{
+ u32 temp;
+
+ pci_read_config_dword(agp_bridge.dev, VIA_AGP3_GARTCTRL, &temp);
+ pci_write_config_dword(agp_bridge.dev, VIA_AGP3_GARTCTRL,
+ temp & ~(1<<7));
+ pci_write_config_dword(agp_bridge.dev, VIA_AGP3_GARTCTRL, temp);
+}
+
static int via_fetch_size(void)
{
int i;
@@ -2857,6 +2923,20 @@
return addr | agp_bridge.masks[0].mask;
}

+static aper_size_info_16 via_generic_agp3_sizes[11] =
+{
+ { 4, 1024, 0, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3|1<<2|1<<1|1<<0 },
+ { 8, 2048, 1, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3|1<<2|1<<1},
+ { 16, 4096, 2, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3|1<<2},
+ { 32, 8192, 3, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3},
+ { 64, 16384, 4, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4},
+ { 128, 32768, 5, 1<<11|1<<10|1<<9|1<<8|1<<5},
+ { 256, 65536, 6, 1<<11|1<<10|1<<9|1<<8},
+ { 512, 131072, 7, 1<<11|1<<10|1<<9},
+ { 1024, 262144, 8, 1<<11|1<<10},
+ { 2048, 524288, 9, 1<<11} /* 2GB <- Max supported */
+};
+
static aper_size_info_8 via_generic_sizes[7] =
{
{256, 65536, 6, 0},
@@ -2873,8 +2953,72 @@
{0x00000000, 0}
};

+static int __init via_generic_setup_agp3 (struct pci_dev *pdev)
+{
+ agp_bridge.masks = via_generic_masks;
+ agp_bridge.aperture_sizes = (void *) via_generic_agp3_sizes;
+ agp_bridge.size_type = U8_APER_SIZE;
+ agp_bridge.num_aperture_sizes = 10;
+ agp_bridge.dev_private_data = NULL;
+ agp_bridge.needs_scratch_page = FALSE;
+ agp_bridge.configure = via_configure_agp3;
+ agp_bridge.fetch_size = via_fetch_size_agp3;
+ agp_bridge.cleanup = via_cleanup_agp3;
+ agp_bridge.tlb_flush = via_tlbflush_agp3;
+ agp_bridge.mask_memory = via_mask_memory;
+ agp_bridge.agp_enable = agp_generic_agp_enable;
+ agp_bridge.cache_flush = global_cache_flush;
+ agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge.insert_memory = agp_generic_insert_memory;
+ agp_bridge.remove_memory = agp_generic_remove_memory;
+ agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge.free_by_type = agp_generic_free_by_type;
+ agp_bridge.agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge.agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge.suspend = agp_generic_suspend;
+ agp_bridge.resume = agp_generic_resume;
+ agp_bridge.cant_use_aperture = 0;
+ return 0;
+}
+
+/*
+ * VIA's AGP3 chipsets do magick to put the AGP bridge compliant
+ * with the same standards version as the graphics card.
+ */
+static void check_via_agp3 (struct pci_dev *pdev)
+{
+ u8 reg;
+
+ pci_read_config_byte(pdev, VIA_AGPSEL, &reg);
+ /* Check AGP 2.0 compatibility mode. */
+ if ((reg & (1<<1))==0)
+ via_generic_setup_agp3(pdev);
+}
+
static int __init via_generic_setup (struct pci_dev *pdev)
{
+ u32 reg;
+
+ /*
+ * Garg, there are KT400s with KT266 IDs.
+ */
+ if (pdev->device == PCI_DEVICE_ID_VIA_8367_0) {
+ /* Is there a KT400 subsystem ? */
+ if (pdev->subsystem_device == PCI_DEVICE_ID_VIA_8377_0) {
+ printk(KERN_INFO PFX "Found KT400 in disguise as a KT266.\n");
+ check_via_agp3(pdev);
+ return 0;
+ }
+ }
+
+ /* If this is an AGP3 bridge, check which mode its in and adjust. */
+ pci_read_config_dword(pdev, VIA_AGPSEL, &reg);
+ if (((reg >> 20) & 0xf) >= 3) {
+ check_via_agp3(pdev);
+ return 0;
+ }
+
agp_bridge.masks = via_generic_masks;
agp_bridge.aperture_sizes = (void *) via_generic_sizes;
agp_bridge.size_type = U8_APER_SIZE;
@@ -2899,10 +3043,7 @@
agp_bridge.suspend = agp_generic_suspend;
agp_bridge.resume = agp_generic_resume;
agp_bridge.cant_use_aperture = 0;
-
return 0;
-
- (void) pdev; /* unused */
}

#endif /* CONFIG_AGP_VIA */[unhandled content-type:application/pgp-signature]
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