Messages in this thread |  | | Date | Sat, 13 Oct 2001 20:24:45 +0200 | From | Manfred Spraul <> | Subject | Re: [PATCH] Pentium IV cacheline size. |
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Linus wrote: > On Sat, 13 Oct 2001, Dave Jones wrote: > > > > Currently, we're using a L1_CACHE_SHIFT value of 7 > > for Pentium 4, which equates to 128 byte cache lines. > > Well, the fact is, that from a SMP standpoint, the 128 bytes is the > correct one: the L2 is 128 bytes wide.
The 128 bytes are split into 2 sectors - I'm not sure if 128 or 64 bytes is appropriate.
<<<<< The L2 cache is a 256K-byte cache that holds both instructions that miss the Trace Cache and data that miss the L1 data cache. The L2 cache is organized as an 8-way set-associative cache with 128 bytes per cache line. These 128-byte cache lines consist of two 64-byte sectors. A miss in the L2 cache typically initiates two 64-byte access requests to the system bus to fill both halves of the cache line. <<<<< http://developer.intel.com/technology/itj/q12001/articles/art_2.htm
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