Messages in this thread | | | From | "Dunlap, Randy" <> | Subject | RE: Updated 2.4 TODO List - more on PCI resources...] | Date | Fri, 13 Oct 2000 16:25:17 -0700 |
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> On Fri, Oct 13, 2000 at 02:22:32PM -0700, Dunlap, Randy wrote: > > I'm not familiar with yenta controllers/devices, > > and I'm not trying to throw you a tasty red herring, > > but... > > > > yenta_config_init() does > > config_writeb(socket, PCI_CACHE_LINE_SIZE, 32); > > > > Is this writing to the CardBus bridge or to the device's > > CacheLineSize register? > > It is writing to the bridge. I think it should probably actually be > L1_CACHE_BYTES/4. I am not sure about the impact of an incorrect > setting. Maybe Linus knows. > > -- Dave
I agree. I would expect it to be 8 instead of 32. Actually I just checked on a new Thinkpad T20 with a TI PCI 1450 CardBus controller *on a different OS* and it is 8.
~Randy
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