Messages in this thread Patch in this message | | | From | Prabhakar <> | Subject | [PATCH v2 04/13] pinctrl: renesas: pinctrl-rzg2l: Allow parsing of variable configuration for all architectures | Date | Tue, 23 Apr 2024 18:58:51 +0100 |
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From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Enable parsing of variable configuration for all architectures. This patch is in preparation for adding support for the RZ/V2H SoC, which utilizes the ARM64 architecture and features port pins with variable configuration.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- RFC->v2 - No change --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 9bb9cc63f9df..c944d94b9a36 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -322,7 +322,6 @@ struct rzg2l_pinctrl { static const u16 available_ps[] = { 1800, 2500, 3300 }; -#ifdef CONFIG_RISCV static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, u64 pincfg, unsigned int port, @@ -339,6 +338,7 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, return 0; } +#ifdef CONFIG_RISCV static const struct rzg2l_variable_pin_cfg r9a07g043f_variable_pin_cfg[] = { { .port = 20, @@ -2299,13 +2299,11 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) if (i && !(i % RZG2L_PINS_PER_PORT)) j++; pin_data[i] = pctrl->data->port_pin_configs[j]; -#ifdef CONFIG_RISCV if (pin_data[i] & PIN_CFG_VARIABLE) pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl, pin_data[i], j, i % RZG2L_PINS_PER_PORT); -#endif pins[i].drv_data = &pin_data[i]; } -- 2.34.1
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