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    Subject[PATCH v2 02/13] dt-bindings: pinctrl: renesas: Document RZ/V2H(P) SoC
    Date
    From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

    Add documentation for the pin controller found on the Renesas RZ/V2H(P)
    (R9A09G057) SoC. The RZ/V2H PFC varies slightly compared to the RZ/G2L
    family:
    - Additional bits need to be set during pinmuxing.
    - The GPIO pin count is different.

    Hence, a SoC-specific compatible string, 'renesas,r9a09g057-pinctrl', is
    added for the RZ/V2H(P) SoC.

    Also, add the 'renesas,output-impedance' property. The drive strength
    setting on RZ/V2H(P) depends on the different power rails coming out from
    the PMIC (connected via I2C). These power rails (required for drive
    strength) can be 1.2V, 1.8V, or 3.3V.

    Pins are grouped into 4 groups:

    Group 1: Impedance
    - 150/75/38/25 ohms (at 3.3V)
    - 130/65/33/22 ohms (at 1.8V)

    Group 2: Impedance
    - 50/40/33/25 ohms (at 1.8V)

    Group 3: Impedance
    - 150/75/37.5/25 ohms (at 3.3V)
    - 130/65/33/22 ohms (at 1.8V)

    Group 4: Impedance
    - 110/55/30/20 ohms (at 1.8V)
    - 150/75/38/25 ohms (at 1.2V)

    The 'renesas,output-impedance' property, as documented, can be
    [0, 1, 2, 3], indicating x1/x2/x3/x4 drive strength.

    As power rail information may not be available very early in the boot
    process, the 'renesas,output-impedance' property is added instead of
    reusing the 'output-impedance-ohms' property.

    Also, allow bias-disable, bias-pull-down and bias-pull-up properties
    as these can be used to configure the pins.

    Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
    ---
    RFC->v2
    - Renamed renesas-rzv2h,output-impedance -> renesas,output-impedance
    - Updated values for renesas,output-impedance
    - Added bias properties
    ---
    .../pinctrl/renesas,rzg2l-pinctrl.yaml | 25 ++++++++++++++++---
    1 file changed, 21 insertions(+), 4 deletions(-)

    diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
    index 881e992adca3..089b3ce61bac 100644
    --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
    +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
    @@ -26,6 +26,7 @@ properties:
    - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
    - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
    - renesas,r9a08g045-pinctrl # RZ/G3S
    + - renesas,r9a09g057-pinctrl # RZ/V2H(P)

    - items:
    - enum:
    @@ -66,10 +67,14 @@ properties:
    maxItems: 1

    resets:
    - items:
    - - description: GPIO_RSTN signal
    - - description: GPIO_PORT_RESETN signal
    - - description: GPIO_SPARE_RESETN signal
    + oneOf:
    + - items:
    + - description: GPIO_RSTN signal
    + - description: GPIO_PORT_RESETN signal
    + - description: GPIO_SPARE_RESETN signal
    + - items:
    + - description: PFC main reset
    + - description: Reset for the control register related to WDTUDFCA and WDTUDFFCM pins

    additionalProperties:
    anyOf:
    @@ -111,6 +116,18 @@ additionalProperties:
    output-high: true
    output-low: true
    line-name: true
    + bias-disable: true
    + bias-pull-down: true
    + bias-pull-up: true
    + renesas,output-impedance:
    + description: |
    + Output impedance for pins on RZ/V2H(P) SoC.
    + 0: Corresponds to x1
    + 1: Corresponds to x2
    + 2: Corresponds to x3
    + 3: Corresponds to x4
    + $ref: /schemas/types.yaml#/definitions/uint32
    + enum: [0, 1, 2, 3]

    - type: object
    additionalProperties:
    --
    2.34.1

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